1. Field of the Invention
The present invention relates to a semiconductor device, especially a MOS transistor for protecting an integrated circuit against electrostatic discharge.
2. Description of the Related Art
Recently, the size of the components of semiconductor integrated circuits has been remarkably reduced, and the minimum line width is now in the range of 1 .mu.m and less which is called the "sub-micron range". In order to produce such microscopic components for integrated circuits, various steps have been taken including increase in the impurity concentration of the impurity regions, and reduction in the thickness of the gate oxide layer, in the thickness of the diffusion layer, and in the diameter of the contact area. Such steps have reduced the breakdown voltage of the gate oxide layer, which has caused the integrated circuit to be weak against electrostatic discharge.
Semiconductor integrated circuits generally include a protection circuit against electrostatic discharge, which is connected with an input pad or an output pad. Referring to FIGS. 22 to 26, a conventional MOS transistor used for protecting a semiconductor integrated circuit against electrostatic discharge will be described.
FIG. 22 is a circuit diagram of a conventional protection circuit 100 against electrostatic discharge. In the protection circuit 100, a transistor section 103 and a resistance 104 are connected in series between an input gate inverter 101 and an input pad 102. The transistor section 103 includes a transistor 105 connected to a power supply voltage and a transistor 106 which is grounded. FIG. 23 is a plan view in section of a conventional MOS transistor used as the transistor 106. FIG. 24 is a cross sectional view of the transistor 106 in FIG. 23 to show section line 24--24 in FIG. 23.
As is shown in FIGS. 23 and 24, the transistor 106 includes a semiconductor substrate 107 formed of p-type silicon. The semiconductor substrate 107 includes a p.sup.+ -type diffusion region 108, a source region 109, a drain region 110, and a channel region 111 sandwiched between the source region 109 and the drain region 110. An island including the p.sup.+ -type diffusion region 108, the source region 109, the drain region 110, and the channel region 111 is surrounded by an isolation region 112 which is also included in the semiconductor substrate 107.
The semiconductor substrate 107 is provided with an insulating film 113 on a surface thereof, and a gate electrode 114 is provided above the channel region 111 with a part of the insulating film 113 interposed therebetween. The insulating film 113 includes contact holes 115, 116 and 117. The contact holes 115 respectively define a plurality of contact regions 118 on the p.sup.+ -type diffusion region 108, and the contact holes 116 respectively define a plurality of contact regions 119 on the source region 109. The contact holes 117 respectively define two contact regions 120a and a plurality of contact regions 120b on the drain region 110. In this specification, the "contact region" refers to a two-dimensional pattern in which a conductive element such as a wire is in contact with an impurity diffusion region such as the source region 109 and the drain region 110. In the insulating film 113, wires 121 and 122 are formed. The wire 121 is electrically connected with the p.sup.+ -type diffusion region 108 and the source region 109 through the contact holes 115 and 116, respectively. The wire 122 is electrically connected with the drain region 110 through the contact holes 117. The wire 122 is also electrically connected to the input pad 102 (FIG. 22), and the wire 121 and the gate electrode 114 are both grounded. The drain region 110 is connected to the input gate inverter 101 (FIG. 22) through the resistance 104.
The protection circuit 100 having the above-described structure operates in the following manner:
An electrostatic voltage is applied to the input pad 102 and is sent to the contact regions 120a and 120b on the drain region 110 through the wire 122 and the contact holes 117. Such an electrostatic charge raises the potential of the drain region 110 and further raises the potential of the semiconductor substrate 107. As a result, an electric current flows so as to operate the source region 109, the drain region 110 and the channel region 111 as a parasitic bipolar transistor 130. The source region 109 acts as an emitter, the drain region 110 acts as a collector, and the channel region 111 acts as a base of the bipolar transistor 130. Accordingly, the electrostatic charge applied to the drain region 110 flows out to the ground through the semiconductor substrate 107, the source region 109, and the wire 121. Thus, the potential of the drain region 110 falls to prevent the input gate inverter 101 from being supplied with a high voltage.
However, the conventional protection circuit 100 has the following problems:
When an electrostatic charge is applied to the input pad 102, the contact regions 120a and 120b on the drain region 110 are supplied with the electrostatic charge through the contact holes 117. The electric current generated by the electrostatic charge flows from the drain region 110 to the source region 109 through the channel region 111. At this point, as is shown in FIG. 25, the electric current is concentrated on the contact regions 120a which are close to the isolation region 112 and the gate electrode 114. Accordingly, the contact regions 120a are easily destroyed. FIG. 26 illustrates the relationship between distance D5 (FIG. 23) between the isolation region 112 and each contact region 120a and the maximum value of the current density in the contact region 120a. As is illustrated in FIG. 26, as distance D5 becomes longer, the maximum value of the current density is raised, and thus the possibility of destruction of the contact regions 120a is increased.
When distance D5 is made shorter in order to prevent the concentration of the current on the contact regions 120a based on the above-mentioned reason, a p-n junction interface 124 (FIG. 25) between a channel stop region 123 provided under the isolation region 112 and the drain region 110 becomes closer to the contact region 120a. Accordingly, the resistance of a part of the drain region 110 which is between the contact region 120a and the isolation region 112 is reduced, and thus the current is concentrated on the p-n junction interface 124 having a low breakdown voltage, thereby easily breaking the p-n junction interface 124.